On April 15 of 2024 Zilog has announced End-of-Life for Z80, one of the most famous 8-bit CPUs of all time.
It is a time for open-source and hardware preservation community to step in with a Free and Open Source Silicon (FOSS) replacement for Zilog Z80.
The first fabrication of FOSS Z80 is scheduled for June of 2024!
On the path to become a silicon proven, pin compatible, open-source replacement for classic Zilog Z80.
FOSS Z80 leverages OpenROAD flow and FOSS 130 nm Skywater PDK to synthesize production ready silicon. Tiny Tapeout infrastructure is used to test and pool design with many others to reduce the cost of physical chip fabrication at Skywater Foundries.
The first iteration of FOSS Z80 silicon
The first iteration is developed with Tiny Tapeout 07 using 130 nm process and fits on a 0.064 mm2 die area. The first fabrication is scheduled for June of 2024 as a part of CI 2406 Shuttle.
The implementation is based around Guy Hutchison’s TV80 Verilog core.
Read documentation for Tiny Tapeout 07 version
Below is the image of GDSII integrated circuit layout for FOSS Z80. It is the result of automatic place-and-route flow in OpenROAD using 130 nm “gates” logic elements.
Add thorough instruction (including ‘illegal’) execution tests ZEXALL to testbench
Compare different implementations: Verilog core A-Z80, Netlist based Z80Explorer
Tapeout with ChipIgnite in QFN44 package
Tapeout with DIP40 package
Create gate-level layouts that would resemble the original Z80 layout, see the original chip dies below. Zilog designed Z80 by manually placing each transistor by hand.
,———.__,———.
–> CLK |6 35| A5 –>
D4 |7 34| A4 –>
D3 |8 33| A3 –>
D5 |9 32| A2 –>
D6 |10 31| A1 –>
VCC |11 30| A0 –>
D2 |12 29| GND
D7 |13 28| /RFSH –>
D0 |14 27| /M1 –>
D1 |15 26| /RESET /INT |16 25| /BUSRQ /NMI |17 24| /WAIT
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